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　 Journal Papers (期刊)
1. C.-Y. Chu, C.-H. Lin, “High-Performance Reconfigurable FEC Architectures for WiMAX,” ITRI SoC Technical Journal, vol. 7, pp. 58−65, Nov. 2007. (in Chinese)
2. X.-Y. Shih, C.-Z. Zhan, C.-H. Lin, and A.-Y. Wu,  “An 8.29mm2 52mW multi-mode LDPC decoder design for mobile WiMAX system in 0.13um CMOS process,” IEEE Jour. Solid-State Circuits, vol. 43, no. 3, pp. 672−683, Mar. 2008. (pdf)
3. F.-M. Li , C.-H. Lin, and A.-Y. Wu,  “Unified convolutional/turbo decoder design using tile-based timing analysis of VA/MAP kernel,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 16, no. 10, pp. 1358−1371, Oct. 2008. (pdf)

4.

 C.-H. Lin, C.-Y. Chen, A.-Y. Wu, and T.-H. Tsai, “Low-power memory-reduced traceback MAP decoding for double-binary convolutional turbo decoder,” IEEE Trans. Circuits and Systems Part I: Regular Paper, Special Issue on ISCAS 2008, vol. 56, no. 5, pp. 1005-1016, May 2009. (Invited) (pdf)
5. C.-H. Lin, C.-Y. Chen, and A.-Y. Wu, “Area-efficient scalable MAP processor design for high-throughput multistandard convolutional turbo decoding,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 19, no. 2, pp. 305-318, Feb. 2011. (pdf)

6.

 C.-H. Lin and C.-C. Wei, “Efficient window-based stopping technique for double-binary turbo decoding,” IEEE Communications Letters, vol. 17, no. 1, pp. 169-172, Jan. 2013. (pdf)
7. C.-H. Lin, T.-H. Huang, C.-C. Chen, and S.-Y. Lin, “Efficient layer stopping technique for layered LDPC decoding,” IET Electronics Letters, vol. 49, no. 16, pp. 994-996, Aug. 2013. (pdf)

8.

 C.-H. Lin, C.-Y. Chen, E.-J. Chang, and A.-Y. Wu, “Reconfigurable parallel turbo decoder design for multiple high-mobility 4G systems,” Journal of Signal Processing Systems, vol. 73, no. 2, pp. 109-122, Nov. 2013. (pdf)

9.

C.-H. Lin and C.-S. Yu, “Multi-mode radix-4 SISO kernel design for turbo/LDPC decoding,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 23, no. 10, pp. 2256-2267, Oct. 2015. (pdf)

10.

 C.-H. Lin, T.-H. Huang, S.-Y. Lin, and Y.-H. Lee, “Design and implementation of operation-reduced LDPC decoder based on a check node stopping scheme,” Journal of Circuits, Systems and Computers, vol. 26, no. 2, pp. 1750028-1-19, Feb. 2017. (pdf)

11.

S.-Y. Lin, H.-Y. Su, and C.-H. Lin, “Thermal-aware mappings with the design trade-offs for 3D dual-mode FEC architecture,” Journal of the Chinese Institute of Engineers, vol. 40, no. 2, pp 149-160, Mar. 2017. (pdf)

12.

 C.-H. Lin and T.-J. Hsieh, “Unified encoder embedded trellis router designs for decoding convolutional and turbo codes,” IEICE Electronics Express, vol. 14, no. 5, pp. 20170028-1-6, Mar. 2017. (pdf)

13.

Y.-H. Lee, C.-H. Lin, C.-C. Chen, S.-Y. Lin, and B.-S. Huang, “The video spatial error concealment algorithm using separately-directional interpolation technique,” Journal of Signal Processing Systems,  vol. 88, no. 1, pp. 13-27, July 2017. (pdf)

14.

 C.-H. Lin, S.-W. Guo, and L.-A. Ou, "Analysis and power evaluation of window-stopped parallel turbo decoding for LTE rate matching," IET Communications, vol. 12 no. 9, pp. 1148-1154, June 2018. (pdf)

15.

C.-H. Lin, Y.-S. Wu, C.-P. Song, “Energy-efficient LDPC codec design using cost-effective early termination scheme,” IET Computers & Digital Techniques, vol. 13, no. 2, pp. 118-125, March 2019. (pdf)

16.

 C.-H. Lin and C.-W. Hsieh, "Low-routing-complexity convolutional/turbo decoder design for iterative detection and decoding receivers," IEEE Trans. Circuits and Systems Part I: Regular Paper, vol. 66, no. 11, pp. 4476-4489, Nov. 2019. (pdf)

17.

C.-H. Lin, W.-M. Liao, J.-W. Liang, P.-H. Chen, C.-E. Ko, C.-H. Yang, and C.-K. Lu, “Denoising performance evaluation of automated age-related macular degeneration detection on optical coherence tomography images,” IEEE Sensors Journal, vol. 21, no. 1, pp. 790-801, Jan. 2021. (pdf)

18.

 W. S. Liew, T. B. Tang, C.-H. Lin, and C.-K. Lu, “Colonic polyp detection using integration of modified deep residual convolutional neural network and ensemble learning approaches,” in Computer Methods and Programs in Biomedicine, vol. 206, p. 106114, July 2021. (pdf)

19.

C.-H. Lin, C.-X. Wang, and C.-K. Lu, “LDPC decoder design using compensation scheme of group comparison for 5G communication systems,” Electronics, Special Issue on Error-Control Coding Algorithms and Architectures for Modern Applications, vol. 10, no. 16, p. 2010, Aug. 2021. (Invited) (pdf)

20.
C. Y. Eu, T. B. Tang, C.-H. Lin, L. H. Lee and C.-K. Lu, “Automatic polyp segmentation in colonoscopy images using a modified deep convolutional encoder–decoder architecture,” Sensors, vol. 21, no. 16, p. 5630, Aug. 2021. (pdf)
　

International Conference Papers (國際會議論文)
1. T.-H. Tsai, C.-H. Lin and S.-Y. Lin, “Low complexity algorithm and architecture design for channel estimation in turbo code,” in Proc. The 46th IEEE Int. Midwest Symp. Circuits and Systems (MWSCAS), vol. 3, pp. 27−30, Dec. 2003.
2. T.-H. Tsai and C.-H. Lin, “A new memory-reduced architecture design for log-MAP algorithm in turbo decoding,” in Proc. The IEEE 6th Circuits and Systems Symp. Emerging Technologies: Frontiers of Mobile and Wireless Communication (MWC), vol. 2, pp. 607−610, May 2004.
3. T.-H. Tsai and C.-H. Lin, “A low complexity channel estimation algorithm and architecture design in turbo codes with early termination techniques,” in Proc. The IEEE 6th Circuits and Systems Symp. Emerging Technologies: Frontiers of Mobile and Wireless Communication (MWC), vol. 1, pp. 213−214, May 2004.

4.

 T.-H. Tsai, C.-H. Lin, and A.-Y. Wu, “A memory-reduced log-Map kernel for turbo decoder,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), vol. 2, pp. 1032−1035, May, 2005.
5. T.-H. Tsai and C.-H. Lin, "A VLSI design of new memory reduction turbo code decoder," in Proc. The 9th IEEE Int. Workshop on Cellular Neural Networks and Their Applications (CNNA), pp. 249−252, May 2005.
6. C.-H. Lin, F.-M. Li, X.-Y. Shih, and A.-Y. Wu, “A triple-mode MAP/VA IP design for advanced wireless communication systems,” in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC), pp. 221−224, Nov. 2005. (Selected Paper for the A-SSCC Press Release: CTIMES、新電子)
7. C.-H. Lin, F.-M. Li, and A.-Y. Wu, “A unified convolutional/turbo kernel design based on triple-mode MAP/VA timing analysis,” in Proc. Int. PhD Student Workshop on SoC (IPS), July 2006.

8.

 F.-M. Li, C.-H. Lin, and A.-Y. Wu, “A new early termination scheme of iterative turbo decoding using decoding threshold,” in Proc. IEEE Workshop on Signal Processing Systems (SiPS), pp. 89-94, Oct. 2006.
9. X.-Y. Shih, C.-Z. Zhan, C.-H. Lin, and A.-Y. Wu, "A 19-mode 8.29mm2 52-mW LDPC decoder chip for IEEE 802.16e system," in Proc. Int. Symp. VLSI Circuits (VLSIC), pp. 16−17, June 2007.
10. C.-H. Lin, C.-Y. Chen, and A.-Y. Wu, “High-throughput 12-Mode CTC decoder for WiMAX standard,” in Proc. IEEE Int. Symp. VLSI Design, Automation, and Test (VLSI-DAT), pp. 216-219, April 2008. (Best Student Paper Award Candidate)
11. C.-H. Lin, C.-Y. Chen, and A.-Y. Wu, “Low-power traceback MAP Decoding for double-binary convolutional turbo decoder,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), pp. 736−739, May 2008. (High Quality Paper Selected in Special Issue of IEEE TCAS-I)
12. C.-Y. Chen, C.-H. Lin, and A.-Y. Wu, “High-throughput dual-mode single/double binary MAP processor design for wireless WAN,” in Proc. IEEE Workshop on Signal Processing Systems (SiPS), pp. 83−87, Oct. 2008.
13. X.-Y. Shih, C.-Z. Zhan, C.-H. Lin, and A.-Y. Wu, “A 52-mW 8.29mm2 19-mode LDPC decoder chip for mobile WiMAX applications,” in Proc. ACM/IEEE Asia and South Pacific Design Automation Conf. (ASP-DAC), pp. 121−122, Jan. 2009.
14. C.-H. Lin, E.-J. Chang, C.-Y. Chen, and A.-Y. Wu, “A 0.16nJ/bit/iteration 3.38mm2 turbo decoder chip for WiMAX/LTE standards,” in Proc. IEEE Int. Symp. Integrated Circuits (ISIC), pp. 178-181, Dec. 2011.  
15. C.-C. Wei and C.-H. Lin, "Window-stopped double-binary turbo decoding based on bit-level detection," in Proc. The 27th Int. Tech. Conf. Circuits/Systems, Computers, and Communications (ITC-CSCC), pp. 1465-1468, July 2012.
16. C.-S. Yu and C.-H. Lin, "Area-efficient radix-4 SISO architecture design for multi-standard turbo/LDPC decoding," in Proc. The 27th Int. Tech. Conf. Circuits/Systems, Computers, and Communications (ITC-CSCC), pp. 1469-1472, July 2012.
17. L.-A. Ou, C.-C. Wei, K.-Y. Hsu, and C.-H. Lin, “Kernel-stopped parallel turbo decoding for HomePlug Green PHY systems,” in Proc. IEEE Asia Pacific Conf. Circuits and Systems (APCCAS), pp. 45−48, Dec. 2012.
18. T.-H. Huang, C.-H. Lin, S.-A. Chou, and S.-W. Guo, “Efficient check nodes stopping technique for MSA-based LDPC decoding,” in Proc. The 28th Int. Tech. Conf. Circuits/Systems, Computers, and Communications (ITC-CSCC), pp. 675-678, July 2013. 
19. S.-W. Guo and C.-H. Lin, “Decision comparison of window-stopped turbo decoding for LTE system,” in Proc. The 28th Int. Tech. Conf. Circuits/Systems, Computers, and Communications (ITC-CSCC), pp. 679-680, July 2013.
20. S.-A. Chou and C.-H. Lin, “QC-LDPC codec design for DSRC Systems with implementation on FPGA board,” in Proc. The 28th Int. Tech. Conf. Circuits/Systems, Computers, and Communications (ITC-CSCC), pp. 1082-1083, July 2013.
21. S.-W. Guo and C.-H. Lin, “Decoding performance of parallelly stopped turbo decoding for LTE rate matching scheme,” in Proc.  Int. Conf. Electronics, Information and Communication (ICEIC), pp. 199-200, Jan. 2014.
22. S.-Y. Lin, and C.-H. Lin, and H.-Y. Su, “Thermal-aware task mapping for reconfigurable channel decoding,”  in Proc. IEEE Int. Symp. Bioelectronics and Bioinformatics (ISBB), pp. 1-4, April 2014.
23. T.-H. Huang, C.-H. Lin, and S.-Y. Lin, “Efficient check-node-stopped LDPC decoder design,” in Proc. IEEE Int. Symp. Consumer Electronics (ISCE), pp. 274-275, June 2014.
24. S.-Y. Lin, C.-H. Lin, and H.-Y. Su, “Thermal-aware kernel mapping for three-dimensional multi-mode channel decoding,” in Proc. IEEE Global Conf. Consumer Electronics (GCCE), pp. 630-631, Oct. 2014.
25. Y.-S. Wu, C.-H. Lin, and S.-Y. Lin, ”Ultra-low complexity early termination scheme for layered LDPC decoding,” in Proc. IEEE Global Conf. Consumer Electronics (GCCE), pp. 711-712, Oct. 2014.
26. S.-Y. Lin, C.-H. Lin, and H.-Y. Su, “Block-based SRAM Architecture and Thermal-Aware Memory Mappings for Three-dimensional Channel Decoding Systems,” in Proc. IEEE Global Conf. Consumer Electronics (GCCE), pp. 277-278, Osaka, Japan, Oct., 2015.
27. C.-H. Lin, C.-H. Chiang, S.-W. Guo, and S.-Y. Lin, “An Enhanced Single-Binary Turbo Decoding Scheme for Turbo  MIMO Systems,” in Proc. IEEE Global Conf. Consumer Electronics (GCCE), pp. 537-538, Oct., 2015.
28. S.-Y. Lin, J.-Y. Lin, and C.-H. Lin, “A reconfigurable near-data systolic array accelerator for the three-dimensional DRAM systems,” in Proc. IEEE Global Conf. Consumer Electronics (GCCE), pp. 107-108, Oct., 2016. (Excellent Paper Award, 2nd Prize)
29. C.-P. Song, C.-H. Lin, and S.-Y. Lin, “Partially-stopped probabilistic min-sum algorithm for LDPC decoding,” in Proc. IEEE Global Conf. Consumer Electronics (GCCE), pp. 135-136, Oct., 2016.
30. Y.-Z. Huang, Y.-H. Hsieh, and C.-H. Lin, “A flexible K-best sphere decoding kernel for configurable antennas and constellations,” in Proc. IEEE Int. Conf. Consumer Electronics-Taiwan (ICCE-TW), pp. 115-116, June, 2017.
31. C.-W. Hsieh and C.-H. Lin, “VLSI implementations of parallel dual-mode MAP decoding for iterative detection and decoding receiver,” in Proc. The 32th Int. Tech. Conf. Circuits/Systems, Computers, and Communications (ITC-CSCC), pp. 217-219, July, 2017. (Best Paper Award)
32. S.-Y. Lin, J.-Y. Lin, and C.-H. Lin, “Cycle-accelerated simulation for three-dimensional near-data processing system with power, temperature, and latency analysis,” in Proc. IEEE Int Conf. Applied System Innovation (ICASI), pp. 124-126, March, 2018.
33. Y.-Z. Huang, C.-H. Lin, and S.-Y. Lin, Operation-reduced enumeration technique for soft-input soft-output iterative sphere decoding,” in Proc. IEEE Int. Conf. Applied System Innovation (ICASI), pp. 1196-1198, March, 2018.
34. X. Ma, C.-H. Lin, and T. Jin, “Phase difference algorithm and its FFT implementation for high-accuracy power system frequency monitoring,” in Proc. IEEE Int. Conf. Consumer Electronics-Taiwan (ICCE-TW), pp. 477-478, May, 2018.
35. C.-H. Lin and J.-K. Shen, “Dual-mode channel decoding kernel design using FBA-based layered LDPC decoding,” in Proc. IEEE Global Conf. Consumer Electronics (GCCE), pp. 181-182, Oct., 2018. (Paper Award Candidate)
36. C.-E. Ko, P.-H. Chen, W.-M. Liao, C.-K. Lu, C.-H. Lin, and J.-W. Liang, “Using a cropping technique or not: impacts on SVM-based AMD detection on OCT images,” in Proc. IEEE Int. Conf. Artificial Intelligence Circuits and Systems (AICAS), pp. 199-200, March, 2019.
37. H.-H. Su, T.-S. Chen, and C.-H. Lin, “Reconfigurable check node unit design of dual-standard LDPC decoding for 60GHz wireless local area network,” in Proc. IEEE Int. Conf. Consumer Electronics-Taiwan (ICCE-TW), pp. 1-2, May, 2019.
38. C.-H. Lin, C.-C. Hong, and C.-W. Hsieh, “Parity-enhanced double-binary turbo decoder for iterative detection and decoding receivers,” in Proc. IEEE Global Conf. Consumer Electronics (GCCE), pp. 534-535, Oct., 2019. ( Excellent Poster Award, Gold Prize)
39. C.-X. Wang and C.-H. Lin, “Improved normalized probabilistic minimum summation algorithm for LDPC decoding,” in Proc. IEEE Int. Conf. Consumer Electronics-Taiwan (ICCE-TW), pp. 1-2, Sept., 2020.
40. C.-H. Yang and C.-H. Lin, “Combined architectures of denoising filter and local binary patterns feature extraction,” in Proc. IEEE Global Conf. Consumer Electronics (GCCE), pp. 209-210, Oct., 2020.
41. H.-Y. You, H.-T. Wei, C.-H. Lin, J.-Y. Ji, Y.-H. Liu, C.-K. Lu, J.-K. Wang, and T.-L. Huang, “An AMDOCT-NET for automated AMD detection under evaluations of different image size, denoising and cropping,” in Proc. IEEE Eurasia Conf. Biomedical Engineering, Healthcare and Sustainability (ECBIOS), pp. 138-142, May 2021.
42. (Accept) C.-H. Cheng and C.-H. Lin*, “Hybrid BP-SC/SCF decoding for polar codes,” in Proc. IEEE Int. Conf. Consumer Electronics-Taiwan (ICCE-TW), June 2021.
　

Patents (專利)
1. 林承鴻, 吳安宇, “渦輪解碼器以及渦輪解碼方法,” 中華民國發明專利 (I339956), 2011/4/1.
2. C.-H. Lin and A.-Y. Wu, “Method and apparatus for turbo code decoding,” U.S. Patent (US 8,230,311 B2), 2012/7/21..
3. 陳俊諭, 林承鴻, 吳安宇, 石韻怡, “通訊資料交錯器之位址產生器與通訊資料解碼電路,” 中華民國專利 (公開編號：201036343).
4. C.-Y. Chen, C.-H. Lin, A.-Y. Wu, and Y.-Y. Shih “Address generator of communication data interleaver and communication data decoding circuit,” U.S. Patent (Application #: 12/419,272).
5. Cheng-Hung Lin, Chih-Chia Wei, Shu-Wei Guo, and Li-An Ou, "Window-Stopped Technique for Turbo Decoding," U.S. Patent (Application #: 13/948,750).
6. 林承鴻, 黃子軒, 周信安,"用於低密度奇偶校驗解碼之層運算停止方法," 中華民國專利 (I504162),  2015/10/11.
7. 林承鴻, 魏志嘉, 郭書瑋, 歐立安, "適用於渦輪解碼之視窗停止技術," 中華民國專利 (I531171), 2016/04/21.
8.

 C.-H. Lin, T.-H. Huang, and S.-A. Chou, "Method for determining layer stoppage in LDPC decoding," U.S. Patent  (US 9,344,116 B2) 2016/5/17.
9. 林承鴻, 謝宗儒, “解碼裝置及方法,” 中華民國發明專利 (I599182), 2017/09/11.
10. Cheng-Hung Lin and Tsung-Ju Hsieh, “Decoding path selection device and method,” U.S. Patent (9,787,331 B1), 2017/10/10.
11. 林書彥, 蘇河雲, 林承鴻, “雙模式錯誤更正碼三維架構之溫度控管設計流程,” 中華民國發明專利 (I615848), 2018/02/21.
12.

Shu-Yen Lin, Ho-Yun Su, and Cheng-Hung Lin, “Thermal-controlled Design Flow for the Three-dimensional Dual-mode Forward Error Correction Architecture,” (Pending) U.S. Patent.